MEC1404 Datasheet, PDF (316/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
21.10.3 WEEK TIMER COMPARE REGISTER
Offset ^08h
Bits
Description
31:28 Reserved
27:0 WEEK_COMPARE
A Week Alarm Interrupt and a Week Alarm Power-Up Event are
asserted when the Week Alarm Counter Register is greater than or
equal to the contents of this register. Reads and writes complete
independently of the state of WT_ENABLE.
Type
R
R/W
Default
Reset
Event
-
FFFFFFFh
-
VBAT_
POR
21.10.4 CLOCK DIVIDER REGISTER
Offset ^0Ch
Bits
Description
Type
31:15 Reserved
R
14:0 CLOCK_DIVIDER
R
Reads of this register return the current state of the Week Timer 15-
bit clock divider.
Default
-
-
Reset
Event
-
VBAT
_POR
21.10.5 SUB-SECOND PROGRAMMABLE INTERRUPT SELECT REGISTER
Offset ^10h
Bits
Description
Type
31:15 Reserved
R
3:0 SPISR
R/W
This field determines the rate at which Sub-Second interrupt events
are generated. Table 21-10, "SPISR Encoding" shows the relation
between the SPISR encoding and Sub-Second interrupt rate.
Default
-
00h
Reset
Event
-
VBAT
_POR
TABLE 21-10: SPISR ENCODING
SPISR Value
Sub-Second Interrupt Rate, Hz
Interrupt Period
0
Interrupts disabled
1
2
500 ms
DS00001956D-page 316
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