MEC1404 Datasheet, PDF (101/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 4-2: SIGNAL DESCRIPTION TABLE (CONTINUED)
Name
LAD2
LAD3
LFRAME#
LRESET#
LCLK
SERIRQ
CLKRUN#
LPCPD#
Direction
Input/Output
Input/Output
Input
Input
Input
Input/Output
Open-Drain Output
Input
Description
Bit[2] of the LPC multiplexed command, address, and
data bus.
Bit[3] of the LPC multiplexed command, address, and
data bus.
Active low signal indicates start of new cycle and termi-
nation of broken cycle.
Active low signal used as LPC Interface Reset. Same as
PCI Reset on host.
Note: LRESET# is typically connected to the host
PCI RESET (PCIRST#) signal.
PCI clock input (PCI_CLK)
Serial IRQ pin used with the LCLK signal to transfer
interrupts to the host.
Clock Control for LCLK
Power Down: Indicates that the device should prepare
for power to be removed from the LPC I/F.
4.4.2 REGISTER INTERFACES
The registers defined for the LPC Interface block are accessible by the various hosts as indicated in Section 4.9, "LPC
Configuration Registers", Section 4.11, "EC-Only Registers"and Section 4.10, "Runtime Registers".
4.5 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
4.5.1 POWER DOMAINS
VTR
4.5.2
Name
Description
The LPC Interface block and registers are
powered by VTR.
CLOCK INPUTS
Name
LCLK
Description
This LPC Interface has a single clock input,
called LCLK.
Note:
The PCI_CLK input to LCLK can run at 24MHz or 33MHz. When the PCI_CLK input is 24MHz the Hand-
shake bit in the EC Clock Control Register must be set to a ‘1’ to capture LPC transactions properly. See
Section 4.11.4, "EC Clock Control Register," on page 129.
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