MEC1404 Datasheet, PDF (193/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 10-13: AGGREGATED GROUP ENABLE SET REGISTER
Offset ^508h
Bits
Description
Type
31:19 Reserved
R
18:0 GIRQ[26:8] Aggregated Group Enable Set
R/W
Each IRQ Vector can be individually enabled to assert an interrupt
event to the EC.
0= Writing a zero has no effect.
1= Writing a one will enable respective IRQi.
Default
-
0h
Reset
Event
-
nSYSR
ST
Reading always returns the current value of the IRQ i VECTOR
ENABLE bit. The state of the IRQ i VECTOR ENABLE bit is deter-
mined by the corresponding IRQ i Vector Enable Set bit and the IRQ
i Vector Enable Clear bit. (0=disabled, 1-enabled)
TABLE 10-14: AGGREGATED GROUP ENABLE CLEAR REGISTER
Offset ^50Ch
Bits
Description
Type
31:19 Reserved
R
18:0 GIRQ[26:8] Aggregated Group Enable Clear
R/W
Each IRQ Vector can be individually disabled to assert an interrupt
event to the EC.
0= Writing a zero has no effect.
1= Writing a one will disable respective IRQi vector.
Default
-
0h
Reset
Event
-
nSYSR
ST
Reading always returns the current value of the IRQ i VECTOR
ENABLE bit. The state of the IRQ i VECTOR ENABLE bit is deter-
mined by the corresponding IRQ i Vector Enable Set bit and the IRQ
i Vector Enable Clear bit. (0=disabled, 1-enabled)
TABLE 10-15: GIRQX ACTIVE REGISTER
Offset ^510h
Bits
Description
Type
31:19 Reserved
R
18:0 GIRQ[26:8] Aggregated Group Active
R
Each read only bit reflects the current state of the IRQ i vector to the
EC. Each bit is the OR’d result of the corresponding GIRQx Interrupt
Result register. If the IRQ i vector is disabled via the GIRQ[26:8]
Aggregated Group Enable Clear register the corresponding IRQ i
vector to the EC is forced to 0. If the IRQ i vector is enabled, the cor-
responding IRQ i vector to the EC represents the current status of the
IRQ event.
Default
-
0h
Reset
Event
-
nSYSR
ST
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DS00001956D-page 193