MEC1404 Datasheet, PDF (181/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
STEPS TO SET UP A PARTICULAR GIRQ GROUPING OF INTERRUPTS TO VECTOR TO AN ISR IN
DISAGGREGATED/JT MODE.
1. Determine a location in code space to contain a mini-jump table, of size 31 entries or less, depending on how
populated a particular GIRQ is (i.e. 15 populated sources = 15 jump table entries in SRAM).
2. Build up to 31 ISRs, one for each interrupt source in this GIRQ. The jump table gets populated with jump instruc-
tions the locations of these ISRs.
3. Program the 17-bit offset for the entry location of the mini-jump table into the GIRQ aggregator control/vector
address register. EBASE must be programmed at 0xbfd0_0000.
4. (optional) Clear all source bits for the interrupts within GIRQ “n”.
5. Enable the individual interrupts within GIRQ “n” that you wish to be interrupt the processor.
6. Enable global interrupts in the processor.
ILLUSTRATIVE SCENARIO:
GIRQ #8 has 31 GPIOs from pins configured to generate interrupts that will be handled by an 31 ISRs labeled
“GIRQ08_GPIO001_handler”, “GIRQ08_GPIO002_handler”, etc.
The 31 GPIOs are named (from GIRQ #8’s bit 0 through bit 30): GPIO001, GPIO002,….,GPIO030.
EBASE is at 0xbfd0_0000. Firmware places the jump table at address 0xbfd0_0500. The jump table gets populated with
jump instructions to the 31 ISRs.
The firmware programs GIRQ #8’s aggregator control to 0x0000_0501 (bits 17:1 are the vector address, bit 0 is the
GIRQ control to aggregate/dis-aggregate).
Firmware then sets each interrupt source priority to, say, 0x0 (2 bits of priority), which corresponds to priority level 1 to
the processor. Then enables all interrupt lines by writing 0xffff_ffff to GIRQ #8’s interrupt “enable set” register address.
If GPIO029 later fires an interrupt to the controller, the controller will send an EIC vector of 0x5e8 with a requested inter-
rupt priority level 1 to the processor. This causes the processor to vector to the 30^th entry in the mini-jump table, which
then jumps to the “GIRQ08_GPIO029_handler” code.
This address: 0x5e8 = vector base + 29*(vector spacing) which is by default 8 bytes.
Later, GPIO002 fires an interrupt to the controller, which causes the controller to send an EIC vector of 0x510 with a
requested interrupt priority level 1 to the processor. This causes the processor to vector to the 3^rd entry in the mini-jump
table, which then jumps to the “GIRQ08_GPIO002_handler” code.
10.11.6 HYBRID MODE
The Hybrid is a combination of the aggregated and disaggregated modes.
Each GIRQ group has the option of operating in either aggregated mode or disaggregated mode. This mode is similar
to the disaggregated mode, except the grouped GIRQs will OR their result through bit 0 of that GIRQ. Each GIRQx[n]
Result Bit is assigned the priority-level that is programmed in the corresponding GIRQx[n] Priority bit. The Priority
Encoder and Decision Logic generates the Vector for the active Result bit with the highest priority. If two or more Result
bits are active with the same priority-level the lowest Result Bit wins.
The following diagram illustrates this selection process.
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DS00001956D-page 181