MEC1404 Datasheet, PDF (484/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
41.4.5.2 Test Mode Entry Codes
TMOD0
Test Mode
Test Mode Entry Code
4D43 4850
“MCHP”
Description
2-wire ICSP
41.4.5.3 Enabling EJTAG Interface
By default the EJTAG interface is disabled. It is gated by the MTAP (MCHP_TAP) controller. MTAP gates all other TAP
controllers TDI so they always operate in BYPASS mode. There are two ISCP commands used to enable/disable the
MTAP gating.
• IR SWTAP_CHIP (5'h04).
- Enables the MTAP and gates the EJTAG interface behind it.
• IR SWTAP (5'h05).
- Disables the MTAP and enables the EJTAG interface behind it.
The steps to enter EJTAG(M14K) are:
1. Drive MCLR# High.
2. Drive ICSP_CLK and ICSP_DAT Low.
3. Drive MCLR# Low.
4. Send down 32 ICSP Clocks with the following pattern on the ICSP_DAT pin (32'h4D434850).
5. Drive MCLR# High.
6. Send down the following IR SWTAP_CHIP (5'h04).
- This will enable the MTAP.
7. Send down the following IR MCHP_CMD (5'h07).
- This puts the DR in MTAP IR: MCHP_CMD
8. Poll 1 byte on the DR Shift until Bit [6] of the byte is 1. Always shift in 0x00.
- The 0x00 shifted in the sub-command Read Status.
- This is polling until the Boot ROM has opened up access to the part (JTAG Security).
9. Send down the following IR SWTAP (5'h05).
- Disables the MTAP and enables the EJTAG behind it.
10. Run EJTAG program here.
41.5 XNOR Chain
41.5.1 OVERVIEW
The XNOR Chain test mode provides a means to confirm that all MEC140X/1X pins are in contact with the motherboard
during assembly and test operations.
An example of an XNOR Chain test structure is illustrated below in . When the XNOR Chain test mode is enabled all
pins, except for the Excluded Pins shown in Section 38.5.2, are disconnected from their internal functions and forced
as inputs to the XNOR Chain. This allows a single input pin to toggle the XNOR Chain output if all other input pins are
held high or low. The XNOR Chain output is the Test Output Pin (XNOR_OUT): GPIO027/KSO00/PVT_IO1.
The tests that are performed when the XNOR Chain test mode is enabled require the board-level test hardware to con-
trol the device pins and observe the results at the XNOR Chain output pin; e.g., as described in Section 41.5.3, "Test
Procedure," on page 485.
41.5.2 EXCLUDED PINS
All pins in the pinout are included in the XNOR chain, except the following:
• Power Pins (VTR, VTR_33_18, VBAT, VREF_CPU)
DS00001956D-page 484
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