MEC1404 Datasheet, PDF (463/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Source
ADC_Repeat_Int
Description
Interrupt signal from ADC controller to EC for Repeated ADC conversion.
38.9 Low Power Modes
The ADC may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
The ADC is designed to conserve power when it is either sleeping or disabled. It is disabled via the Activate Bit and
sleeps when the ADC_SLEEP_EN signal is asserted. The sleeping state only controls clocking in the ADC and does
not power down the analog circuitry. For lowest power consumption, the ADC Activate bit must be set to ‘0.’
38.10 Description
FIGURE 38-2:
ADC BLOCK DIAGRAM
ADC BLOCK
VREF
ADC Reading Registers
Host Interface
reading
Latch
Control
Logic
10-bit reading value
ADC
Analog Inputs

MUX


ADC_Single_Int
ADC_Repeat_Int
ADC_SLEEP_EN
ADC_CLK_REQ
Control
The MEC140X/1X features successive approximation Analog to Digital Converter with up to sixteen channels. The ADC
architecture features excellent linearity and converts analog signals to 10 bit words. Conversion takes less than 12
microseconds per 10-bit word. The sixteen channels are implemented with a single high speed ADC fed by a sixteen
input analog multiplexer. The multiplexer cycles through the sixteen voltage channels, starting with the lowest-numbered
channel and proceeding to the highest-number channel, selecting only those channels that are programmed to be
active.
The input range on the voltage channels spans from 0V to the external voltage reference. With an external voltage ref-
erence of 3.0V, this provides resolutions of 2.9mV. The accuracy of any voltage reading depends on the accuracy and
stability of the voltage reference input.
Note: The ADC pins are 3.3V tolerant.
The ADC conversion cycle starts either when the Start_Single bit in the ADC to set to 1 or when the ADC Repeat Timer
counts down to 0. When the Start_Single is set to 1 the conversion cycle converts channels enabled by configuration
bits in the ADC Single Register. When the Repeat Timer counts down to 0 the conversion cycle converts channels
enabled by configuration bits in the ADC Repeat Register. When both the Start_Single bit and the Repeat Timer request
conversions the Start_Single conversion is completed first.
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DS00001956D-page 463