MEC1404 Datasheet, PDF (150/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^30h
Bits
Description
Type
6 RX_TRANSFER_ENABLE
R/W
This bit enables the receive function of the SPI interface.
1=Receive is enabled. Data received from the SPI Slave is stored
in the Receive Buffer
0=Receive is disabled
5:4 TX_DMA_ENABLE
R/W
This bit enables DMA support for Transmit Transfer. If enabled,
DMA will be requested to fill the FIFO until either the interface
reaches TRANSFER_LENGTH or the DMA sends a termination
request. The size defined here must match DMA programmed
access size.
1=DMA is enabled.and set to 1 Byte
2=DMA is enabled and set to 2 Bytes
3=DMA is enabled and set to 4 Bytes
0=DMA is disabled. All data in the Transmit Buffer must be emptied
by firmware
3:2 TX_TRANSFER_ENABLE
R/W
This field bit selects the transmit function of the SPI interface.
3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out
only 1's. The Transmit Buffer will not be used
2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will send out
only 0's. The Transmit Buffer will not be used.
1=Transmit Enabled. Data will be fetched from the Transmit Buffer
and sent out on the MOSI or IO Bus.
0=Transmit is Disabled. No data is sent. This will cause the MOSI
be to be undriven, or the IO bus to be undriven if Receive is
also disabled.
1:0 INTERFACE_MODE
R/W
This field sets the transmission mode. If this field is set for Dual
Mode or Quad Mode then either TX_TRANSFER_ENABLE or
RX_TRANSFER_ENABLE must be 0.
3=Reserved
2=Quad Mode
1=Dual Mode
0=Single/Duplex Mode
Default
0h
Reset
Event
RESET
0h
RESET
0h
RESET
0h
RESET
6.11.12 QMSPI DESCRIPTION BUFFER 1 REGISTER
The format for this register is the same as the format o the QMSPI Description Buffer 0 Register.
6.11.13 QMSPI DESCRIPTION BUFFER 2 REGISTER
The format for this register is the same as the format o the QMSPI Description Buffer 0 Register.
DS00001956D-page 150
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