MEC1404 Datasheet, PDF (110/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
The LPC interface can claim up to a 4 kB block of memory addresses and map them to the internal address space. The
location of the block of memory in the 32-bit internal space, as well as access to it, is controlled by the EC, using the
SRAM Memory Host Configuration Register.
The block of memory in the internal 32-bit address space must start on any size-byte address boundary. For example,
if the memory is 4k bytes than it is only relocatable on 4k byte boundaries.
CLAIMING LPC MEMORY TRANSACTIONS
A Base Address Register will match an LPC Memory address, and thus the device will claim the LPC bus cycle, if the
following relation holds:
bit (LPC Address & ~(BAR.2^SIZE-1) == (BAR.Host_Address & ~(BAR.2^SIZE-1)) && (BAR.Valid == 1)
If the BAR matches, the LPC cycle will be claimed by the device. The LPC request will be translated to an AHB address
according to the following formula:
AHB Address = (BAR.AHB_Base & ~(BAR.2^SIZE-1)) | (LPC_Address & (BAR.2^SIZE-1))
The mapping is also illustrated in FIGURE 4-4:
FIGURE 4-4:
AHB ADDRESS BIT MAPPING
31
23
0
LPC Address
31
23
31
23
12
0
0 0000000
0
AHB Base
Size (1 to 12) address
bits passed through
from LPC Address to
AHB address
12
0
AHB Address
FORWARDING SRAM MEMORY TRANSACTIONS
The LPC interface can claim up to a 4 kB block of memory addresses and map them to the internal address space.
The firmware programs the base address of the internal memory space in SRAM Memory Host Configuration Register,
which is mapped to the LPC memory address programmed by the host in the SRAM Memory BAR register. The firmware
also programs the size of the memory to be accessed. The LPC block uses the size field to determine which memory
addresses to claim (see Section , "Claiming LPC Memory Transactions," on page 110), as well as to prevent read-
ing/writing an unmapped internal memory location.
4.8.3 CONFIGURATION PORT
The LPC Host can access the Chip’s Configuration Registers through the Configuration Port when CONFIG MODE is
enabled. The device defaults to CONFIG MODE being disabled.
Note: The data read from the Configuration Port Data register is undefined when CONFIG MODE is not enabled.
DS00001956D-page 110
 2015 - 2016 Microchip Technology Inc.