MEC1404 Datasheet, PDF (103/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
4.6 Interrupts
This section defines the Interrupt Sources generated from this block.
Source
Description
LPC_WAKE
LPC_INTERNAL_ERR
This signal is asserted when the LPC interface detects LPC traffic. If
enabled, it may be used to wake the 48 MHz Ring Oscillator when the
chip is in a sleep state.
Note: This interrupt is grouped with other Wake-Only events in
GIRQQ16 and GIRQ22.
The LPC_INTERNAL_ERR event is sourced by bit D0 of the Host Bus
Error Register.
4.7 Low Power Modes
The LPC Controller may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
The LPC Controller will deassert its clock required signal when it is commanded to sleep and it is not processing an LPC
transaction, thereby allowing the 48 MHz Ring Oscillator to be turned off. If a subsequent transaction is detected on the
LPC interface, the LPC Controller will assert the LPC_WAKE signal to the JTVIC Controller. If enabled, this event will
wake the 48 MHz Ring Oscillator.
4.8 Description
This LPC Controller is compliant with the Intel® Low Pin Count (LPC) Interface Specification, v1.1. Section 4.8.1, "LPC
Controller Description" further clarifies which LPC Interface features have been implemented and qualifies any system
specific requirements.
The LPC Controller claims only LPC transactions targeted for one of its peripherals. Section 4.8.2, on page 106,
describes the mechanism for Claiming and Forwarding Transactions for Supported LPC Cycles. LPC transactions may
be used to configure the chip and to access registers during operation. The mechanism to configure the chip is
described in Section 4.8.3, "Configuration Port," on page 110.
The LPC memory cycles may also be used to access the Base Address Registers of certain devices as well as internal
SRAM.
Once configured, the LPC peripherals implemented as logical devices on chip may use the SERIRQ to notify the host
of an event. See Section 4.8.4, "Serial IRQs," on page 112.
4.8.1 LPC CONTROLLER DESCRIPTION
The following sections qualify the LPC features implemented according to the LPC Specification.
4.8.1.1 Cycle Types Supported
The following cycle types are supported by the LPC Interface Controller. All other cycles that it does not support are
ignored.
TABLE 4-5: LPC CYCLE TYPES SUPPORTED
Cycle Type
I/O Read
I/O Write
Memory Read
Memory Write
Transfer Size
1 byte
1 byte
1 byte
1 byte
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