MEC1404 Datasheet, PDF (439/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
34.8.1 AHB ERROR CONTROL
Offset ^14h
Bits
Description
7:1 Reserved
0 AHB_ERROR_DISABLE
0: EC memory exceptions are enabled.
1: EC memory exceptions are disabled.
Type
R
RW
Default
-
0h
Reset
Event
-
nSYSRST
34.8.2 COMPARATOR CONTROL
Offset ^18h
Bits
Description
7:6 Reserved
5 Comparator 1 Threshold Input Select
0: Pin
1: DAC1
4 Comparator 1 Enable
0: Disable Comparator 1 for operation
1: Enable Comparator 1 operation.
3 Reserved
2 Comparator 0 Configuration Locked
0: Configuration Not Locked. Bits[2:0] are Read-Write
1: Configuration Locked. Bits[2:0] are Read-Only
Type
R
RW
Default
-
0h
Reset
Event
-
nSYSRST
RW
0h
nSYSRST
R
R/W1X
-
-
0h
nSYSRST
1 Comparator 0 Threshold Input Select
0: Pin
1: DAC0
RW or
0h
RO
(Note 1)
0 Comparator 0 Enable
0: Disable Comparator 0 for operation
1: Enable Comparator 0 operation.
RW or
0h
RO
(Note 1)
Note 1: These bits become Read-Only by writing bit 2 Comparator 0 Configuration Locked bit
nSYSRST
nSYSRST
34.8.3 JTAG ENABLE
Offset ^20h
Bits
Description
31:2 Reserved
1 Boot ROM Configuration Ready
Type
R
R/W
This bit indicates to the ICSP debugger when the Boot ROM has
finished its configuration sequence. The state of this bit is reflected
in the MCHP_CMD <0x07> Read Status register.
0 = Boot ROM has not finished configuration sequence
1 = Boot ROM has finished configuration sequence.
Default
-
0b
Reset
Event
-
nSYSRST
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DS00001956D-page 439