MEC1404 Datasheet, PDF (115/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
4.8.4.4 Latency
Latency for IRQ/Data updates over the SERIRQ bus in bridge-less systems with the minimum IRQ/Data Frames of 17
will range up to 96 clocks (3.84S with a 25 MHz LCLK or 2.88s with a 33 MHz LCLK).
Note:
If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary
or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asyn-
chronous buses.
4.8.4.5 EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an
EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host
interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to
delay EOIs and ISR Reads to the interrupt controller by the same amount as the SERIRQ Cycle latency in order to
ensure that these events do not occur out of order.
4.8.4.6 AC/DC Specification Issue
All Serial IRQ agents must drive/sample SERIRQ synchronously related to the rising edge of LCLK. The SERIRQ pin
uses the electrical specification of the PCI bus. Electrical parameters will follow the PCI Local Bus Specification, Rev.
2.2 definition of “sustained tri-state.”
4.8.4.7 Reset and Initialization
The SERIRQ bus uses LRESET# as its reset signal and follows the PCI bus reset mechanism. The SERIRQ pin is tri-
stated by all agents while LRESET# is active. With reset, SERIRQ slaves and bridges are put into the (continuous) Idle
mode. The host controller is responsible for starting the initial SERIRQ cycle to collect system’s IRQ/Data default values.
The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SERIRQ
cycles. It is the host controller’s responsibility to provide the default values to the 8259’s and other system logic before
the first SERIRQ cycle is performed. For SERIRQ system suspend, insertion, or removal application, the host controller
should be programmed into Continuous (IDLE) mode first. This is to ensure the SERIRQ bus is in Idle state before the
system configuration changes.
4.8.4.8 SERIRQ Interrupts
The LPC Controller routes Logical Device interrupts onto SIRQ stream frames IRQ[0:15]. Routing is controlled by the
SIRQ Interrupt Configuration Registers. There is one SIRQ Interrupt Configuration Register for each accessible SIRQ
Frame (IRQ); all 16 registers are listed in Table 4-13, "SIRQ Interrupt Configuration Register Map".
The format for each SIRQ Interrupt Configuration Register is described in Section 4.9.2.1, "SIRQ Configuration Register
Format," on page 119. Each Logical Device can have up to two LPC SERIRQ interrupts. When the device is polled by
the host, each SIRQ frame routes the level of the Logical Device interrupt (selected by the corresponding SIRQ Interrupt
Configuration Register) to the SIRQ stream.
4.8.4.9 SERIRQ Routing
Each SIRQ Interrupt Configuration Register controls a series of multiplexers which route to a single Logical Device inter-
rupt as illustrated in FIGURE 4-7: SIRQ Routing Internal Logical Devices on page 117. The following table defines the
Serial IRQ routing for each logical device implemented in the chip.
TABLE 4-10: LOGICAL DEVICE SIRQ ROUTING TABLE
SIRQ INTERRUPT
CONFIGURATION REGISTER
LOGICAL DEVICE INTERRUPT SOURCE
SELECT
0
0
DEVICE
0
0
FRAME
C
9
LOGICAL DEVICE
(BLOCK INSTANCE - Note 26.2)
LPC Interface (Configuration Port)
Mailbox Interface
INTERRUPT SOURCE
EC_IRQ
MBX_Host_SIRQ
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