MEC1404 Datasheet, PDF (164/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
10.0 JUMP TABLE VECTORED INTERRUPT CONTROLLER (JTVIC)
10.1 Overview
The Jump Table Vectored Interrupt Controller (JTVIC) works in conjunction with the MIPS32^ M14K^TM Processor Inter-
rupt Interface. The interrupt events are synchronous events that may be serviced in either Aggregated Mode or Disag-
gregated mode. The JTVIC block presents the Vector for the highest priority interrupt pending. The priority-level is
firmware selectable.
A subset of the interrupts are classified as wake events that can be recognized without a running clock, e.g., while the
MEC140X/1X is in sleep state. These asynchronous events are routed to the chip’s clock generation logic and are used
to resume the clock’s operation from a sleep state and wake the processor.
10.2 References
• MIPS32^ M14K^TM Processor Core Data Sheet, April 30, 2012.
• MIPS32^ M14K^TM Software Users Manual, Document Number: MD00668, Revision 02.03, April 30, 2012.
• MIPS32^ M14K^TM Integrator’s Guide, Document Number: MD00667, Revision 02.03, April 30, 2012.
10.3 Terminology
Term
IPL
PIPL
Definition
Interrupt Priority Level
Pending Interrupt Priority Level
10.4 Interface
This block is designed to be accessed internally via a registered host interface.
FIGURE 10-1:
I/O DIAGRAM OF BLOCK
Host Register Interface
Interrupt Sources
EIC Interrupt Interface
Wake Events
Power, Clocks and Reset
Jump Table Vectored Inter-
rupt Controller (JTVIC)
10.5 Host Register Interface
The registers defined for the Jump Table Vectored Interrupt Controller (JTVIC) Interface are accessible by the various
hosts as indicated in Section 10.12, "JTVIC Registers".
DS00001956D-page 164
 2015 - 2016 Microchip Technology Inc.