MEC1404 Datasheet, PDF (275/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
17.6 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
17.6.1 POWER DOMAINS
VTR
17.6.2
Name
CLOCK INPUTS
Description
This Power Well is used to power the registers and logic in this block.
Name
1.8432MHz_Clk
24MHz_Clk
17.6.3 RESETS
Description
The UART requires a 1.8432 MHz ± 2% clock input for baud rate
generation.
24 MHz ± 2% clock input. This clock may be enabled to generate the
baud rate, which requires a 1.8432 MHz ± 2% clock input.
Name
Description
nSYSRST
nSIO_RESET
RESET
This reset is asserted when VTR is applied.
This is an alternate reset condition, typically asserted when the main
power rail is asserted.
This reset is determined by the POWER bit signal. When the power bit
signal is 1, this signal is equal to nSIO_RESET. When the power bit
signal is 0, this signal is equal to nSYSRST.
17.7 Interrupts
This section defines the Interrupt Sources generated from this block.
UART
Source
Description
The UART interrupt event output indicates if an interrupt is pending. See
Table 17-8, “Interrupt Control Table,” on page 284.
UART
Source
Description
The UART interrupt event output indicates if an interrupt is pending. See
Table 17-8, “Interrupt Control Table,” on page 284.
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DS00001956D-page 275