MEC1404 Datasheet, PDF (165/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
10.6 Interrupt Sources
All the chip’s interrupt sources are routed to the Jump Table Vectored Interrupt Controller (JTVIC) GIRQx Source Reg-
isters. The list of interrupt sources is defined in Table 10-2, “Interrupt Source, Enable Set, Enable Clear, and Result Bit
Assignments,” on page 169.
10.7 EIC Interrupt Interface
The Jump Table Vectored Interrupt Controller (JTVIC) is designed to generate interrupts to the Embedded Controller’s
External Interrupt Controller (EIC) interface. This IP block aggregates all the chip’s interrupt Sources (defined in
Table 10-2, “Interrupt Source, Enable Set, Enable Clear, and Result Bit Assignments,” on page 169), determines the
highest priority interrupt that is active, and generates the Offset Vector used to jump to the respective IRQ Handler.
10.7.1 EIC INTERRUPT SIGNALS
Name
Direction
Description
Interrupt Request
Vector_Address
RIPL
Output
Output
Output
Signal to the processor that an interrupt request is pending
Offset appended to processor EBASE address to create
pointer to IRQ handler.
Note: The processor EBASE must be programmed on a
256k Byte boundary.
Requested Interrupt Priority Level.
10.8 Wake Events
All interrupt sources that indicate they are wake-capable generate an asynchronous wake event to the chip’s sleep con-
trol logic to restore the oscillator to the fully operational state. Wake-capable signals do not require the internal oscillator
to be running.
10.9 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
10.9.1 POWER
VTR
Name
10.9.2 CLOCKS
Description
The logic and registers implemented in this block are powered by this
power well.
Name
48 MHz Ring Oscillator
Description
Clock used for register read/write access.
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