MEC1404 Datasheet, PDF (92/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
3.9.10 OSCILLATOR ID REGISTER (CHIP_OSC_ID)
Offset ^30h
Bits
31:9 RESERVED
8 OSC_LOCK
Oscillator Lock Status
7:0 Reserved
Description
Type
RES
R
R
Default
Reset
Event
0h
nSYSR
ST
N/A
nSYSR
ST
3.9.11 PCR CHIP SUB-SYSTEM POWER RESET STATUS (CHIP_PWR_RST_STS)
Offset ^34h
Bits
Description
Type
31:12 RESERVED
11 PCICLK_ACTIVE
This bit monitors the state of the PCI clock input. This status bit
detects edges on the clock input but does not validate the fre-
quency.
0: The 33MHz PCI clock input is not present.
1: The 33MHz PCI clock is present.
10 32K_ACTIVE
This bit monitors the state of the external 32K clock input. This sta-
tus bit detects edges on the clock input but does not validate the
frequency.
0: The external 32K clock input is not present.
1: The external 32K clock input is present.
9 VBAT_LOW
This bit is set if VBAT is below 2V when VTRGD is asserted. It is
also set on the rising edge of VTRGD if a new coin was inserted
while VTR was off.
8:7 RESERVED
6 VTR reset status
Indicates the status of nSYSRST.
0 = No reset occurred since the last time this bit was cleared.
1 = A reset occurred.
RES
R
R
R
RES
R/WC
Default
Reset
Event
-
nSYSR
ST
-
nSYSR
ST
-
nSYSR
ST
1h
nSYSR
ST
DS00001956D-page 92
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