MEC1404 Datasheet, PDF (283/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
17.11.7 INTERRUPT IDENTIFICATION REGISTER
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority
interrupt exist. They are in descending order of priority:
1. Receiver Line Status (highest priority)
2. Received Data Ready
3. Transmitter Holding Register Empty
4. MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Iden-
tification Register (refer to TABLE 17-8:). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indi-
cates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new
interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.
Offset ^02h
Bits
Description
Type
7:6 FIFO_EN
R
These two bits are set when the FIFO CONTROL Register bit 0
equals 1.
5:4 Reserved
R
3:1 INTID
R
These bits identify the highest priority interrupt pending as indi-
cated by Table 17-8, "Interrupt Control Table". In non-FIFO mode,
Bit[3] is a logic “0”. In FIFO mode Bit[3] is set along with Bit[2] when
a timeout interrupt is pending.
0 IPEND
R
This bit can be used in either a hardwired prioritized or polled envi-
ronment to indicate whether an interrupt is pending. When bit 0 is a
logic ‘0’ an interrupt is pending and the contents of the IIR may be
used as a pointer to the appropriate internal service routine. When
bit 0 is a logic ‘1’ no interrupt is pending.
Default
0h
Reset
Event
RESET
-
-
0h
RESET
1h
RESET
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