MEC1404 Datasheet, PDF (431/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
33.6 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
33.6.1 POWER DOMAINS
VTR
33.6.2
Name
CLOCK INPUTS
Description
This Power Well is used to power the registers and logic in this block.
Name
48 MHz Ring Oscillator
33.6.3 RESETS
Description
This is the clock source for Port 80 block logic.
Name
Description
nSYSRST
This signal is asserted when VTR is low, PWRGD is low, or Host Inter-
face is reset.
33.7 Interrupts
This section defines the Interrupt Sources generated from this block.
BDP_INT
Source
Description
The Port 80 BIOS Debug Port generates an EC interrupt when the
amount of data in the Port 80 FIFO equals or exceeds the FIFO Thresh-
old defined in the Configuration Register.
The interrupt signal is always generated by the Port 80 block if the block
is enabled; the interrupt is enabled or disabled in the Interrupt Aggrega-
tor.
33.8 Low Power Modes
The Port 80 block may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
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DS00001956D-page 431