MEC1404 Datasheet, PDF (139/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^00h
Bits
Description
Type
10 CHPA_MISO
R/W
Clock phase of the Master data in. In normal SPI modes, this field
must be programmed with the same value as CHPA_MOSI in this
register.
If CPOL=0:
1=Data are captured on the rising edge of the SPI clock
0=Data are captured on the falling edge of the SPI clock
If CPOL=0:
1=Data are captured on the falling edge of the SPI clock
0=Data are captured on the rising edge of the SPI clock
9 CHPA_MOSI
R/W
Clock phase of the Master data out. In normal SPI modes, this field
must be programmed with the same value as CHPA_MISO in this
register.
If CPOL=0:
1=Data changes on the falling edge of the SPI clock
0=Data changes on the rising edge of the SPI clock
If CPOL=0:
1=Data changes on the rising edge of the SPI clock
0=Data changes on the falling edge of the SPI clock
8 CPOL
R/W
Polarity of the SPI clock line when there are no transactions in pro-
cess.
1=SPI Clock starts High
0=SPI Clock starts Low
7:2 Reserved
R
1 SOFT_RESET
W
Writing this bit with a ‘1’ will reset the Quad SPI block. It is self-
clearing.
0 ACTIVATE
R/W
1=Enabled. The block is fully operational
0=Disabled. Clocks are gated to conserve power and the output sig-
nals are set to their inactive state
Default
0h
Reset
Event
RESET
0h
RESET
0h
RESET
-
-
0h
nSYSR
ST
0h
RESET
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DS00001956D-page 139