MEC1404 Datasheet, PDF (353/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
24.10 DMA Main Registers
The addresses of each register listed in these tables are defined as a relative offset to the “Base Address” defined in
the DMA Main Register Base Address Table. The Base Address indicates where the first register can be accessed in a
particular bank of registers.
TABLE 24-3: DMA MAIN REGISTER BASE ADDRESS TABLE
Instance Name
DMA Controller
Channel
Number
Main Block
Host
EC
Address Space
32-bit internal
address space
Base Address
0000_2400h
TABLE 24-4: DMA MAIN REGISTER SUMMARY
Offset
00h
04h
REGISTER NAME (Mnemonic)
DMA Main Control Register
DMA Data Packet Register
24.10.1 DMA MAIN CONTROL REGISTER
Offset ^00h
Bits
Description
Type
7:2 Reserved
R
1 SOFT_RESET
W
Soft reset the entire module.
This bit is self-clearing.
0 ACTIVATE
Enable the blocks operation.
R/WS
1=Enable block. Each individual channel must be enabled sepa-
rately.
0=Disable all channels.
24.10.2 DMA DATA PACKET REGISTER
Default
-
0b
Reset
Event
-
-
0b
DMA_
RESET
Offset ^04h
Bits
Description
31:0 DATA_PACKET
Debug register that has the data that is stored in the Data Packet.
This data is read data from the currently active transfer source.
Type
R
Default
0000h
Reset
Event
-
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DS00001956D-page 353