MEC1404 Datasheet, PDF (348/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
24.0 INTERNAL DMA CONTROLLER
24.1 Features
• Supports Memory-to-Memory BYTE, WORD, and DWORD transfers
• Used to Perform DMA transactions for DMA capable hardware IP blocks
• Supports 7 DMA Channels that may be configured for any Hardware Device or Memory transfer
• Channel 0 Supports CRC-32 generation
24.2 Introduction
The Internal DMA Controller transfers data to/from the source from/to the destination. The firmware is responsible for
setting up each channel. Afterwards either the firmware or the hardware may perform the flow control. The hardware
flow control exists entirely inside the source device. Each transfer may be 1, 2, or 4 bytes in size, so long as the device
supports a transfer of that size. Every device must be on the internal 32-bit address space.
24.3 References
No references have been cited for this chapter
24.4 Terminology
TABLE 24-1: TERMINOLOGY
Term
DMA Transfer
Data Packet
Channel
Device
Master Device
Slave Device
Definition
This is a complete DMA Transfer which is done after the Master Device
terminates the transfer, the Firmware Aborts the transfer or the DMA
reaches its transfer limit.
A DMA Transfer may consist of one or more data packets.
Each data packet may be composed of 1, 2, or 4 bytes. The size of the
data packet is limited by the max size supported by both the source and
the destination. Both source and destination will transfer the same num-
ber of bytes per packet.
The Channel is responsible for end-to-end (source-to-destination) Data
Packet delivery.
A Device may refer to a Master or Slave connected to the DMA Channel.
Each DMA Channel may be assigned one or more devices.
This is the master of the DMA, which determines when it is active.
The Firmware is the master while operating in Firmware Flow Control.
The Hardware is the master while operating in Hardware Flow Control.
The Master Device in Hardware Mode is selected by DMA Channel Con-
trol:Hardware Flow Control Device. It is the index of the Flow Control
Port.
The Slave Device is defined as the device associated with the targeted
Memory Address.
DS00001956D-page 348
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