MEC1404 Datasheet, PDF (159/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
8.4.1.1 Mapping ICSP to EJTAG Interface
The JTAG debug interface signals are connected internally to the ICSP block. The ICSP block converts the 2-wire ICSP
interface into standard EJTAG signaling. port that is connected to the external pin interface.
FIGURE 8-2:
ICSP-TO-EJTAG
ICSP_CLK
ICSP_DAT
MCLR#
ICSP Controller
PWR
MTAP
JTAG
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_RST#
MIPS M14K
EJTAG
Note: The MCLR# is pulled up internally and requires no external logic.
For a description of the ICSP Controller see Section 41.4, "ICSP Controller," on page 479.
8.4.2 AHB INTERFACE
A Processor-to-Memory Translator has been appended to the ISRAM and DSRAM interfaces. This translator will pass
traffic to either the ISRAM, DSRAM, or AHB interface based on the address of the access. The AHB Interface is the
embedded controller’s interface to the EC Address Space (i.e., 32-bit internal address space) that is not used as EC
Code or Data space (e.g., Peripheral Registers).
The MIPS32 M14K core can have at most one access pending on the AHB at one time. It can perform 8-bit, 16-bit and
32-bit loads and stores on the AHB.
Possible AHB bus errors are described in Section 8.4.2.1, "AHB & Code/Data Bus Errors," on page 159. The processor
responds to a bus error with Memory Error exception, except where noted.
8.4.2.1 AHB & Code/Data Bus Errors
AHB bus requests can be terminated with an AHB bus error. The handling of bus errors by the EC is described in Chap-
ter 4, Exceptions and Interrupts in the M14K Core, of the MIPS32^® M14K™ Processor Core Software User’s Manual,
Document Number: MD00668, Revision 02.03, April 30, 2012.
Bus errors may be caused by:
• Code accesses to a memory location outside of the Code/ROM memory range will generate a processor excep-
tion
• Data accesses to out-of-bounds memory location in data region (0xBFD18000 - 0xBFFF_FFFF) returns garbage
(no processor exception).
• EC I/O requests to undefined EC Address memory locations via the System AHB Interface.will generate a proces-
sor exception
8.4.3 SYSTEM INTERFACE
TABLE 8-2: SYSTEM INTERFACE SIGNAL DESCRIPTION TABLE
Signal Name
SI_RP
SI-EXL
Direction
Output
Output
Description
Connected
at Chip-Level
The SI_RP signal represents the state of the RP bit (27) in
No
the CP0 Status register. This signal may be used at the chip-
level to decide whether to enter a lower power state.
The SI_EXL signal represents the state of the EXL bit (1) in
No
the CP0 Status register. This signal may be used for throttling
the clock after a wake event.
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DS00001956D-page 159