MEC1404 Datasheet, PDF (257/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
The PCOBF register is also readable; the value read back on bit 0 of the register always reflects the present value of
the PCOBF output. If PCOBFEN = 1, then this value reflects the output of the firmware latch in the PCOBF Register. If
PCOBFEN = 0, then the value read back reflects the in-process status of write cycles to the HOST2EC Data Register
(i.e., if the value read back is high, the host interface output data register has just been written to). If OBFEN=0, then
KIRQ is driven inactive (low).
16.10.2 AUXOBF DESCRIPTION
If enabled by the bit OBFEN, the bit AUXOBF is multiplexed onto MIRQ. The AUXOBF/MIRQ signal is a system interrupt
which signifies that the EC has written to the EC_HOST Data / AUX Data Register. On power-up, after nSYSRST,
AUXOBF is reset to 0. AUXOBF will normally reflects the status of writes to EC EC AUX Data Register (EC-Only offset
Ch). AUXOBF is cleared by hardware on a read of the Host Data Register. If OBFEN=0, then MIRQ is driven inactive
(low).
MIRQ is normally selected as IRQ12 for mouse support.
Firmware can also directly control the AUXOBF output signal, similar to the mechanism it can use to control PCOBF.
Firmware control is active when AUXH is ‘0’. Firmware sets AUXOBF high by writing a “1” to the AUXOBF field of the
EC Keyboard Status Register. Firmware must also clear AUXOBF by writing a “0” to the AUXOBF field.
TABLE 16-2: OBFEN AND PCOBFEN EFFECTS ON KIRQ
OBFEN
0
1
1
PCOBFEN
X
0
1
KIRQ is inactive and driven low
KIRQ = PCOBF (status of writes to HOST2EC Data Register)
KIRQ = PCOBF (status of writes to PCOBF Register)
TABLE 16-3: OBFEN AND AUXH EFFECTS ON MIRQ
OBFEN
0
1
1
AUXH
X
0
1
MIRQ is inactive and driven low
MIRQ = AUXOBF (status of writes to EC AUX Data Register)
MIRQ = AUXOBF (status of writes to AUXOBF in EC Keyboard Status Register)
16.11 Legacy Port92/GATEA20 Support
The MEC140X/1X supports LPC I/O writes to port HOST I/O address 92h as a quick alternate mechanism for generating
a CPU_RESET pulse or controlling the state of GATEA20. The Port92/GateA20 logic has a separate Logical Device
Number and Base Address register (see Section 16.16, "Legacy Port92/GATEA20 Configuration Registers" and Section
16.17, "Legacy Port92/GATEA20 Runtime Registers". The Base Address Register for the Port92/GateA20 Logical
Device has only one writable bit, the Valid Bit, since the only I/O accessible Register has a fixed address.
The Port 92 Register resides at HOST I/O address 92h and is used to support the alternate reset (ALT_RST#) and alter-
nate GATEA20 (ALT_A20) functions. This register defaults to 00h on assertion of nSIO_RESET.
Setting the Port92 Enable bit (Port 92 Enable Register) enables the Port92h Register. When Port92 is disabled, by clear-
ing the Port92 Enable bit, then access to this register is completely disabled (I/O writes to host 92h are ignored and I/O
reads float the system data bus SD[7:0]).
16.11.1 GATE A20 SPEEDUP
The MEC140X/1X contains on-chip logic support for the GATEA20 hardware speed-up feature. GATEA20 is part of the
control required to mask address line A20 to emulate 8086 addressing.
In addition to the ability for the host to control the GATEA20 output signal directly, a configuration bit called SAEN in the
Keyboard Control Register is provided; when set, SAEN allows firmware to control the GATEA20 output. When SAEN
is set, a 1 bit register (GATEA20 Control Register) controls the GATEA20 output.
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