MEC1404 Datasheet, PDF (345/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
23.7 DMA Interface
This block is designed to communicate with the Internal DMA Controller. This feature is defined in the SMBus Controller
Core Interface specification (See Ref [1]).
Note: For a description of the Internal DMA Controller implemented in this design see Chapter 24.0, "Internal DMA
Controller".
23.8 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
23.8.1 POWER DOMAINS
VTR
Name
23.8.2 CLOCK INPUTS
Description
This power well sources all of the registers and logic in this block, except
where noted.
Name
48 MHz Ring Oscillator
16MHz_Clk
23.8.3 RESETS
nSYSRST
Name
23.9 Interrupts
Description
This is the clock signal drives the SMBus controller core. The core also
uses this clock to generate the SMB_CLK on the pin interface.
This is the clock signal is used for baud rate generation.
Description
This reset signal resets all of the registers and logic in the SMBus
controller core.
SMB_WAKE
Source
SMB
Description
The SMBus_Wake event is generated when a valid SMBus START
sequence is detected on the SMBus pin interface.
SMBus Activity Interrupt Event
23.10 Low Power Modes
The SMBus Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry. If an
SMBus START is detected while the SMBus block is in a low power state the block will generate the SMB_WAKE event.
In enabled in the Jump Table Vectored Interrupt Controller (JTVIC) on page 164, this event may be used to wake the
chip from a low power sleep state.
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