MEC1404 Datasheet, PDF (195/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
11.6 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
11.6.1 POWER DOMAINS
VTR
Name
11.6.2 CLOCK INPUTS
Description
The logic and registers implemented in this block reside on this single
power well.
5Hz_Clk
Name
11.6.3 RESETS
Description
The 5Hz_Clk clock input is the clock source to the Watchdog Timer
functional logic, including the counter.
nSYSRST
Name
Description
Power on Reset to the block. This signal resets all the register and logic
in this block to its default state.
WDT Event
Source
11.7 Description
Description
Pulse generated when WDT expires. This signal is used to reset the
embedded controller and its subsystem.
The event is cleared after an nSYSRST.
11.7.1 WDT OPERATION
11.7.1.1 WDT Activation Mechanism
The WDT is activated by the following sequence of operations during normal operation:
1. Load the WDT Load Register with the count value.
2. Set the WDT Enable bit in the WDT Control Register.
The WDT Activation Mechanism starts the WDT decrementing counter.
11.7.1.2 WDT Deactivation Mechanism
The WDT is deactivated by the clearing the WDT Enable bit in the WDT Control Register. The WDT Deactivation Mech-
anism places the WDT in a low power state in which clock are gated and the counter stops decrementing.
11.7.1.3 WDT Reload Mechanism
The WDT must be reloaded within periods that are shorter than the programmed watchdog interval; otherwise, the WDT
will underflow and a WDT Event will be generated and the WDT Status bit will be set in the WDT Control Register. It is
the responsibility of the user program to continually execute code which reloads the watchdog timer, causing the counter
to be reloaded
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