MEC1404 Datasheet, PDF (255/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
16.5 Host Interface
The 8042 interface is accessed by host software via a registered interface, as defined in Section 16.13, "Configuration
Registers" and Section 16.14, "Runtime Registers".
16.6 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
16.6.1 POWER DOMAINS
VTR
16.6.2
Name
CLOCK INPUTS
Description
This Power Well is used to power the registers and logic in this block.
1MHz
16.6.3
Name
RESETS
Description
Clock used for the counter in the CPU_RESET circuitry.
Name
Description
nSYSRST
VCC_PWRGD
PCI_RESET#
nSIO_RESET
This reset is asserted when VTR is applied.
This signal is asserted when the main power rail is asserted.
This signal is asserted when LRESET# is asserted.
This signal is asserted when VTR is low, PWRGD is low, or LRESET#
is asserted.
16.7 Interrupts
This section defines the Interrupt Sources generated from this block.
KIRQ
MIRQ
IBF
OBF
Source
Source
Description
This interrupt source for the SIRQ logic, representing a Keyboard inter-
rupt, is generated when the PCOBF status bit is ‘1’.
This interrupt source for the SIRQ logic, representing a Mouse interrupt,
is generated when the AUXOBF status bit is ‘1’.
Description
Interrupt generated by the host writing either data or command to the
data register
Interrupt generated by the host reading either data or aux data from the
data register
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DS00001956D-page 255