MEC1404 Datasheet, PDF (512/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
FIGURE 43-8:
BC-LINK WRITE TIMING
BC_CLK
BC_DAT ^{Bit n-1}
t_OH
t_C
Bit n
t_OS
TABLE 43-10: BC-LINK MASTER TIMING DIAGRAM PARAMETERS
Name
Description
MIN
t_c(High Speed)
High Spec BC Clock Frequency
23.5
High Spec BC Clock Period
40.8
t_OS
BC-Link Master DATA output setup time
before rising edge of CLK.
t_OH
BC-Link Master Data hold time after falling
edge of CLK
t_IS
BC-Link Master DATA input setup time
15
before rising edge of CLK.
t_IH
BC-Link Master DATA input hold time after
0
rising edge of CLK.
TYP
24
41.67
MAX
24.5
42.5
t_c-t_OH-
MAX
10
Units
MHz
ns
nsec
nsec
nsec
nsec
Note 43-11
Note 43-12
The (t_IH in TABLE 43-10:) BC-Link Master DATA input must be stable before next rising edge of CLK.
The BC-Link Clock frequency is limited by the application usage model (see BC-Link Master
Section 31.5, Signal Description). The BC-Link Clock frequency is controlled by the BC-Link Clock
Select Register. The tc(High Speed) parameter implies both BC-link master and companion devices
are located on the same circuit board and a high speed clock setting is possible.
Note: The timing budget equation is as follows for data from BC-Link slave to master:
Tc > TOD(master-clk) + Tprop(clk) +TOD(slave) + Tprop(slave data) + TIS(master).
DS00001956D-page 512
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