MEC1404 Datasheet, PDF (219/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

FIGURE 13-3:
MAILBOX SIRQ AND SMI ROUTING
Mailbox Registers
MBX_Host_SIRQ
MBX_Host_SMI
MEC140X/1X
SIRQ Mapping
SIRQ
GPIO
nSMI
Pin Control Register
13.10.3 EC MAILBOX CONTROL
The HOST-to-EC Mailbox Register and EC-to-Host Mailbox Register are designed to pass commands between the host
and the EC. If enabled, these registers can generate interrupts to both the Host and the EC.
The two registers are not dual-ported, so the HOST BIOS and Keyboard BIOS must be designed to properly share these
registers. When the host performs a write of the HOST-to-EC Mailbox Register, an interrupt will be generated and seen
by the EC if unmasked. When the EC writes FFh to the Mailbox Register, the register resets to 00h, providing a simple
means for the EC to inform the host that an operation has been completed.
When the EC writes the EC-to-Host Mailbox Register, an SMI may be generated and seen by the host if unmasked.
When the Host CPU writes FFh to the register, the register resets to 00h, providing a simple means for the host to inform
that EC that an operation has been completed.
Note:
The protocol used to pass commands back and forth through the Mailbox Registers Interface is left to the
System designer. Microchip can provide an application example of working code in which the host uses the
Mailbox registers to gain access to all of the EC registers.
13.11 Runtime Registers
The registers listed in the Runtime Register Summary table are for a single instance of the Mailbox. The addresses of
each register listed in this table are defined as a relative offset to the host “Base Address” defined in the Runtime Reg-
ister Base Address Table.
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DS00001956D-page 219