MEC1404 Datasheet, PDF (223/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

13.12.2 EC-TO-HOST MAILBOX REGISTER
MEC140X/1X
Offset ^4h
MBX_ ^01h
INDEX
Bits
Description
7:0 EC_HOST_MBOX
An EC write to this register will set bit EC_WR in the SMI Interrupt
Source Register to ‘1b’. If enabled, this will’ generate a Host SMI.
This register is cleared when written with FFh.
Type
R
13.12.3 SMI INTERRUPT SOURCE REGISTER
Default
0h
Reset
Event
nSYSR
ST
Offset ^8h
MBX_ ^02h
INDEX
Bits
Description
Type
7:1 EC_SWI
EC Software Interrupt. An SIRQ to the Host is generated when any
bit in this register when this bit is set to ‘1b’ and the corresponding
bit in the SMI Interrupt Mask Register register is ‘1b’.
This field is Read/Write when accessed by the EC at the EC offset.
When written through the Host Access Port, each bit in this field is
cleared when written with a ‘1b’. Writes of ‘0b’ have no effect.
0 EC_WR
EC Mailbox Write. This bit is set automatically when the EC-to-
Host Mailbox Register has been written. An SMI or SIRQ to the
Host is generated when n this bit is ‘1b’ and the corresponding bit
in the SMI Interrupt Mask Register register is ‘1b’.
This bit is automatically cleared by a read of the EC-to-Host Mail-
box Register through the Host Access Port.
Host
Access
Port:
R/WC
EC:
R/W
Host
Access
Port:
R
EC:
-
This bit is read-only when read through the Host Access Port. It is
neither readable nor writable directly by the EC when accessed at
the EC offset.
Default
0h
0h
Reset
Event
nSYSR
ST
nSYSR
ST
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DS00001956D-page 223