MEC1404 Datasheet, PDF (315/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
21.10.1 CONTROL REGISTER
Offset ^00h
Bits
Description
Type
31:7 Reserved
R
6 POWERUP_EN
R/W
This bit controls the state of the Power-Up Event Output and
enables Week POWER-UP Event decoding in the VBAT-Powered
Control Interface on page 462 . See Section 2.5.8, "Power-Up Event
Output," on page 307 for a functional description of the POWER-
UP_EN bit.
1=Power-Up Event Output Enabled
0=Power-Up Event Output Disabled and Reset
5 BGPO
R/W
VBAT-powered General Purpose Output Control that is used as part
of the VBAT-Powered Control Interface.
1=Output high
0=Output low
4:1 Reserved
R
0 WT_ENABlLE
R/W
The WT_ENABLE bit is used to start and stop the Week Alarm
Counter Register and the Clock Divider Register.
The value in the Counter Register is held when the WT_ENABLE bit
is not asserted (‘0’) and the count is resumed from the last value
when the bit is asserted (‘1’).
The 15-Bit Clock Divider is reset to 00h and the RTC/Week Alarm
Interface is in its lowest power consumption state when the WT_EN-
ABLE bit is not asserted.
Default
-
00h
Reset
Event
-
VBAT
_POR
00h
VBAT
_POR
-
-
00h
VBAT
_POR
21.10.2 WEEK ALARM COUNTER REGISTER
Offset ^04h
Bits
Description
31:28 Reserved
27:0 WEEK_COUNTER
While the WT_ENABLE bit is ‘1’, this register is incremented at a 1
Hz rate. Writes of this register may require one second to take
effect. Reads return the current state of the register. Reads and
writes complete independently of the state of WT_ENABLE.
Type
R
R/W
Default
-
00h
Reset
Event
-
VBAT
_POR
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DS00001956D-page 315