MEC1404 Datasheet, PDF (145/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^10h
Bits
Description
Type
3 RECEIVE_BUFFER_ERROR
R/WC
1=Underflow error occurred (attempt to read from an empty Receive
Buffer)
0=No underflow occurred
2 TRANSMIT_BUFFER_ERROR
R/WC
1=Overflow error occurred (attempt to write to a full Transmit Buffer)
0=No overflow occurred
1 DMA_COMPLETE
This field has no meaning if DMA is not enabled.
R/WC
This bit will be set to ‘1’ when the DMA controller asserts the DONE
signal to the SPI controller. This occurs either when the SPI con-
troller has closed the DMA transfer, or the DMA channel has com-
pleted its count. If both Transmit and Receive DMA transfers are
active, then this bit will only assert after both have completed. If
CLOSE_TRANSFER_ENABLE is enabled, DMA_COMPLETE and
TRANSFER_COMPLETE will be asserted simultaneously. This
status is not inhibited by the description buffers, so it can fire on all
valid description buffers while operating in that mode.
1=DMA completed
0=DMA not completed
0 TRANSFER_COMPLETE
In Manual Mode (neither DMA nor Description Buffers are
enabled), this bit will be set to ‘1’ when the transfer matches
TRANSFER_LENGTH.
R/WC
If DMA Mode is enabled, this bit will be set to ‘1’ when DMA_COM-
PLETE is set to ‘1’.
In Description Buffer Mode, this bit will be set to ‘1’ only when the
Last Buffer completes its transfer.
In all cases, this bit will be set to ‘1’ if the STOP bit is set to ‘1’ and
the controller has completed the current 8 bits being copied.
1=Transfer completed
0=Transfer not complete
Default
0h
Reset
Event
RESET
0h
RESET
0h
RESET
0h
RESET
 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 145