MEC1404 Datasheet, PDF (118/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 4-12: CONFIGURATION REGISTER SUMMARY
Register Name
LPC Activate Register
SIRQ Configuration Register Format
I/O Base Address Registers (IO_BARs)
SRAM Memory BAR
SRAM Memory BAR Configuration
Device Memory Base Address Registers (DEV_MEM_BARs)
Offset
30h
40h - 4Fh
60h - 9Fh
See TABLE 4-
14:
A0h
A4h
C0h - FFh
See TABLE 4-
15:
Size
8
8
32
32
32
48
Notes
4.9.1 LPC ACTIVATE REGISTER
The LPC Activate Register controls the LPC device itself. The Host can shut down the LPC Logical Device by clearing
the Activate bit, but it cannot restart the LPC interface, since once the LPC interface is inactive the Host has no access
to any registers on the device. The Embedded Controller can set or clear the Activate bit at any time.
Offset ^30h
Bits
Description
Type
7:1 RESERVED
0 ACTIVATE
1= Activate
When this bit is 1, the LPC Logical Device is powered and func-
tional.
0= Deactivate
When this bit is 0, the logical device is powered down and inactive.
Except for the LPC Activate Register itself, clocks to the block are
gated and the LPC Logical Device will permit the ring oscillator to
be shut down (see Section 4.11.4, "EC Clock Control Register," on
page 129). LPC bus output pads will be tri-stated.
RES
R/W
Default
-
0b
Reset
Event
-
nSYSR
ST
APPLICATION NOTE: The bit in the LPC Activate Register should not be written ‘0’ to by the Host over LPC.
4.9.2 SERIAL IRQ CONFIGURATION REGISTERS
The LPC Controller implements 16 IRQ channels that may be configured to be asserted by any logical device.
• For a description of the SIRQ Configuration Register format see Table 4-13, “SIRQ Interrupt Configuration Regis-
ter Map,” on page 119.
• For a summary of the SIRQ IRQ Configuration registers implemented see Table 4-14, “I/O Base Address Regis-
ters,” on page 122.
• For a list of the SIRQ sources see Table 4-10, “Logical Device SIRQ Routing Table,” on page 115.
DS00001956D-page 118
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