MEC1404 Datasheet, PDF (209/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
12.9.10 INTERRUPT SOURCE MSB REGISTER
Offset ^09h
Bits
Description
Type
7:0 EC_SWI_MSB
EC Software Interrupt Most Significant Bits. These bits are soft-
ware interrupt bits that may be set by the EC to notify the host of an
event. The meaning of these bits is dependent on the firmware
implementation.
Each bit in this field is cleared when written with a ‘1b’. The ability
to clear the bit can be disabled by the EC. if the corresponding bit
in the Host Clear Enable Register is set to ‘0b’. This may be used
by firmware for events that cannot be cleared while the event is still
active.
12.9.11 INTERRUPT MASK LSB REGISTER
R/WC
Default
0h
Reset
Event
nSYSR
ST
Offset ^0Ah
Bits
Description
Type
7:1 EC_SWI_EN_LSB
R/W
EC Software Interrupt Enable Least Significant Bits. Each bit that is
set to ‘1b’ in this field enables the generation of a Host_SWI_Event
interrupt by the corresponding bit in the EC_SWI field in the Inter-
rupt Source LSB Register.
0 EC_WR_EN
R/W
EC Mailbox Write.Interrupt Enable. If this bit is ‘1b’, the interrupt
generated by bit EC_WR in the Interrupt Source LSB Register is
enabled to generate a EC-to-Host interrupt event.
12.9.12 INTERRUPT MASK MSB REGISTER
Default
0h
Reset
Event
nSYSR
ST
0h
nSYSR
ST
Offset ^0Bh
Bits
Description
Type
7:0 EC_SWI_EN_MSB
R/W
EC Software Interrupt Enable Most Significant Bits. Each bit that is
set to ‘1b’ in this field enables the generation of a Host_SWI_Event
interrupt by the corresponding bit in the EC_SWI field in the Inter-
rupt Source MSB Register.
Default
0h
Reset
Event
nSYSR
ST
 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 209