MEC1404 Datasheet, PDF (77/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
There are two ways to command the chip blocks to enter sleep.
1. Assert the Sleep All bit located in the System Sleep Control Register (SYS_SLP_CNTRL) on page 86
2. Assert all the individual block sleep enable bits
Blocks will only enter sleep after their sleep signal is asserted and they no longer require the 48 MHz Ring Oscillator
source. Each block has a corresponding clock required status bit indicating when the block has entered sleep. The gen-
eral operation is that a block will keep the 48 MHz Ring Oscillator on until it completes its current transaction. Once the
block has completed its work, it deasserts its clock required signal. Blocks like timers, PWMs, etc. will deassert their
clock required signals immediately. See the individual block Low Power Mode sections to determine how each individual
block enters sleep.
3.7.3 DETERMINING WHEN THE CHIP IS SLEEPING
There are two methods to verify the chip’s clock has stopped, which indicates the device is in one of these three sleep
states: SYSTEM HEAVY SLEEP 2, SYSTEM HEAVY SLEEP 3, SYSTEM DEEPEST SLEEP. Note that the 48 MHz Ring
Oscillator continues to run in the SYSTEM HEAVY SLEEP 1 state to minimize wake latency.
Option 1: TST_CLK_OUT pin
The TST_CLK_OUT, which is located on the GPIO157/LED0/TST_CLK_OUT pin, is used to route the internal 48 MHz
Ring Oscillator to a pin. If the clock is toggling the chip is in the full on running state. if the clock is not toggling the chip
has entered the programmed sleep state.
Option 2: MTAP Test Bit
Bit [1] SLEEPING has been implemented in the MTAP registers (MCHP_CMD <0x07>) to allow the firmware developer
to determine if the chip is sleeping via the ICSP debug port. This MTAP command does not require the 48 MHz Ring
Oscillator to be clocking and therefore will not change the chip’s sleep state. Note that all of the ICSP debugger com-
mands that access the processor JTAG port will bring the device out of sleep.
3.7.4 WAKING THE CHIP FROM SLEEPING STATE
The chip will remain in the configured sleep state until it detects either a wake event, an ICSP access, or a full VTR
POR. All the wake-capable interrupt events are defined in the Section 10.0, "Jump Table Vectored Interrupt Controller
(JTVIC)". They are identified as Wake Events in Table 10-2, “Interrupt Source, Enable Set, Enable Clear, and Result Bit
Assignments,” on page 169.
3.7.4.1 Wake-Only Events
Two GIRQ registers have been reserved for special wake events. GIRQ16 is used for wake-events that do not require
software processing. These events are used to turn the clock on so the peripherals can start processing the data. There
is no information for the firmware to process. When GIRQ16 is active the firmware can simply clear the source and
return to the sleep state. GIRQ22 is a duplicate of GIRQ16 with one major difference. GIRQ22 does not generate a pro-
cessor interrupt. It only wakes the 48 MHz Ring Oscillator so the peripherals can start processing the data.
Example: LPC I/O Traffic targeting EMI block.
The LPC Interface detects traffic on the bus and requires the clock to be on to process the incoming data. If GIRQ22 is
enabled, the LPC block will be able to autonomously receive data for the programmed I/O ranges without processor
intervention. Once the data is loaded into the HOST-to-EC Mailbox Register the Host-to-EC IRQ will trigger an interrupt
to the embedded controller to service this command.
An alternate solution would be to enable the GIRQ16 LPC interrupt. The process is similar, except the embedded con-
troller will receive an interrupt for the LPC activity, as well as the Host-to-EC IRQ, and will need to clear this event also.
3.7.4.2 ICSP Debugger Wake Events
The ICSP Debugger will cause the chip to wake and run debug code. Auto Clear Sleep and Sleep Debug bits have been
implemented to allow firmware to re-enter sleep following a debug access. It is recommended to set these bits to ‘1’ as
described in the following Application Note.
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