MEC1404 Datasheet, PDF (167/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
FIGURE 10-2:
TOP-LEVEL BLOCK DIAGRAM OF INTERRUPT GENERATION LOGIC
GIRQ aggregator
control, priority, and vector address
GIRQ # “n”
Priority Encoder/
decision logic and
EIC interface
CPU read/write data bus
Int src/result
/enable
registers
interrupt sources
32
requested shadow set
requested interrupt priority level
GIRQ aggregator
control, priority, and vector address
GIRQ # “n + 1”
interrupt vector address
CPU read/write data bus
interrupt sources
32
Int src/result
/enable
registers
10.11.3 WAKE-CAPABLE INTERRUPT EVENTS
Wake-capable interrupts are listed in Section 10.11.4, "List of Interrupt Events," on page 169 with a designation of ‘Yes’
in the Wake Event column
All interrupts, except GIRQ22, generate an EC Interrupt event. They are routed to source bits that are synchronized to
the 48 MHz Ring Oscillator. If enabled, the Interrupt Result is fed into the Priority Encoder/Decision Logic, which gen-
erates the interrupt vector to the EIC Interrupt Interface.
Some Interrupts, which are labeled Wake-Capable, are also routed as Wake Events to the Chip’s Wake Logic. These
are asynchronous events that are used to resume the 48 MHz Ring Oscillator operation from a sleep state and wake
the processor.
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DS00001956D-page 167