MEC1404 Datasheet, PDF (480/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
41.4.2 POWER, CLOCKS, AND RESET
41.4.2.1 Power Domains
Name
Description
VTR
The ICSP Controller logic and registers are implemented on this single
power domain.
41.4.2.2 Clocks
The ICSP port runs internally from the externally-provided ICSP_CLK clock pulses only. There is no requirement for
ICSP_CLK to be constantly running.
41.4.2.3 Reset
nSYSRST
JTAG_RST#
Name
Description
Power On Reset for ICSP controller and registers
Active-Low Test Reset Signal. Generated by toggling ICSP_MCLR low.
41.4.3 ICSP TEST MODES
The ICSP block supports TMOD0 .
• TMOD0 supports 2-wire ICSP JTAG
TMOD0 converts 2-wire ICSP signaling (Clock and Data) to standard 4-wire JTAG signaling (TCK, TMS, TDI and TDO).
Doing this conversion has a cost of four clocks, therefore four ICSP_CLK pulses is equivalent to one JTAG clock (i.e.,
4x slowdown).
FIGURE 41-1:
ICSP-TO-JTAG CONVERSION TIMING (4 CLOCKS)
ICSP Clock
ICSP Data
TCK
TMS/TDI
TDO
TDI TMS
TDO
TDI
TDO
Description
The ICSP will resume
driving on the next
clock cycle.
ICSP Data is undriven at this
time to turn around the bus.
DS00001956D-page 480
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