MEC1404 Datasheet, PDF (281/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
17.11.4 PROGRAMMABLE BAUD RATE GENERATOR MSB REGISTER
Offset ^{01h (DLAB=1)}
Bits
Description
Type
Default
Reset
Event
7 BAUD_CLK_SEL
R/W
0h
RESET
0=If CLK_SRC is ‘0’, the baud clock is derived from the
1.8432MHz_Clk. If CLK_SRC is ‘1’, this bit has no effect
1=If CLK_SRC is ‘0’, the baud clock is derived from the 24MHz_Clk.
If CLK_SRC is ‘1’, this bit has no effect
6:0 BAUD_RATE_DIVISOR_MSB
R/W
See Section 17.9.1, "Programmable Baud Rate".
0h
RESET
17.11.5 INTERRUPT ENABLE REGISTER
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible
to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits
of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identi-
fication Register and disables any Serial Port interrupt out of the MEC140X/1X. All other system functions operate in
their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Reg-
ister are described below.
Offset ^{01h (DLAB=0)}
Bits
Description
Type
7:4 Reserved
R
3 EMSI
R/W
This bit enables the MODEM Status Interrupt when set to logic “1”.
This is caused when one of the Modem Status Register bits
changes state.
2 ELSI
R/W
This bit enables the Received Line Status Interrupt when set to
logic “1”. The error sources causing the interrupt are Overrun, Par-
ity, Framing and Break. The Line Status Register must be read to
determine the source.
1 ETHREI
R/W
This bit enables the Transmitter Holding Register Empty Interrupt
when set to logic “1”.
0 ERDAI
R/W
This bit enables the Received Data Available Interrupt (and timeout
interrupts in the FIFO mode) when set to logic “1”.
Default
-
0h
Reset
Event
-
RESET
0h
RESET
0h
RESET
0h
RESET
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DS00001956D-page 281