MEC1404 Datasheet, PDF (88/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^24h
Bits
Description
22 TIMER16_3 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note: on page 81.
21 TIMER16_2_Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note: on page 81.
20 BC-Link1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
19 BC-Link0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
18 LED2 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
17 LED1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
16 LED0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
15 RESERVED
14 SMB2 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
13 SMB1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
12 RTOS Timer Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
11 KEYSCAN Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
10 HTIMER Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
9 Quad SPI Master Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
DS00001956D-page 88
Type
R/W
Default
0h
Reset
Event
nSYSR
ST
R/W
0h
nSYSR
ST
R/W
R/W
R/W
R/W
R/W
RES
R/W
R/W
R/W
R/W
R/W
R/W
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
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