MEC1404 Datasheet, PDF (104/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
When the LPC Controller detects a transaction targetted for this device it will claims and forward that transaction as
defined in Section 4.8.2, "Claiming and Forwarding Transactions for Supported LPC Cycles," on page 106.
LPC I/O Cycles
The system host may use LPC I/O cycles to read/write the I/O mapped configuration and runtime registers implemented
in this device. See the Intel® Low Pin Count (LPC) Interface Specification, v1.1, Section 5.2 for definition of LPC I/O
Cycles.
LPC Memory Cycles
The system host may use LPC memory cycles to access memory mapped registers and internal RAMs implemented in
this device. See the Intel® Low Pin Count (LPC) Interface Specification, v1.1, Section 5.1 for definition of LPC Memory
Cycles.
4.8.1.2 LAD[3:0] Fields
The LAD[3:0] signals support multiple fields for each protocol as defined in section 4.2.1 LAD[3:0] of the Intel® Low Pin
Count (LPC) Interface Specification, v1.1. The following sections further qualify the fields supported.
Wait SYNCs on LPC
LPC transactions that access registers located on the device will require a minimum of two wait SYNCs on the LPC bus.
The number of SYNCs may be larger if the internal bus is in use by the embedded controller, of if the data referenced
by the host is not present in a register. The device always uses Long Wait SYNCs, rather than Short Wait SYNCs, when
responding to an LPC bus request.
Note: All LPC transactions are synchronized to the LCLK and will complete with a maximum of 8 wait states,
unless otherwise noted.
ERROR SYNCs on LPC
The device does not issue ERROR SYNC cycles.
4.8.1.3 LPC Clock Run and LPC Power Down Behavior
Using LPCPD#
The device tolerates the LPCPD# signal going active and then inactive again without LRESET# going active. This is a
requirement for notebook power management functions.
The Intel® Low Pin Count (LPC) Interface Specification, v1.1, Section 8.2 states that “After LPCPD# is de-asserted, the
LPC interface may be reset dependent upon the characteristics of system reset signal connected to LRESET#.” This
text must be qualified for mobile systems where it is possible that when exiting a "light" sleep state (ACPI S1, APM POS),
LPCPD# may be asserted but the LPC Bus power may not be removed, in which case LRESET# will not occur. When
exiting a "deeper" sleep state (ACPI S3-S5, APM STR, STD, soft-off), LRESET# will occur.
The LPCPD# pin is implemented as a “local” powergood for the LPC bus in the device. It is not to be used as a global
powergood for the chip. It is used to minimize the LPC power dissipation.
Prior to going to a low-power state, the system asserts the LPCPD# signal. LPCPD# goes active at least 30 microsec-
onds prior to the LCLK signal stopping low and power being shut to the other LPC interface signals. Upon recognizing
LPCPD# active, there are no further transactions on the LPC interface.
Using CLKRUN#
CLKRUN# is used to indicate the status of LCLK as well as to request that a stopped clock be started. See FIGURE
4-2: CLKRUN# System Implementation Example on page 105, an example of a typical system implementation using
CLKRUN#.
LCLK Run Support can be enabled and disabled via SIRQ_MODE as shown in Table 4-6, "LPC Controller CLKRUN#
Function". When the SIRQ_MODE is ‘0,’ Serial IRQs are disabled, the CLKRUN# pin is disabled, and the affects of Inter-
rupt requests on CLKRUN# are ignored. When the SIRQ_MODE is ‘1,’ Serial IRQs are enabled, the CLKRUN# pin is
enabled, and the CLKRUN# support related to Interrupts requests as described in the section below is enabled.
The CLKRUN# pin is an open drain output and input. Refer to the PCI Mobile Design Guide Rev 1.0 for a description
of the CLKRUN# function. If CLKRUN# is sampled “high”, LCLK is stopped or stopping. If CLKRUN# is sampled “low”,
LCLK is starting or started (running).
DS00001956D-page 104
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