MEC1404 Datasheet, PDF (201/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Source
HOST-TO-EC
Description
Interrupt source for the Interrupt Aggregator, generated by the host writ-
ing the HOST-to-EC Mailbox Register.
12.7 Low Power Modes
The Embedded Memory Interface (EMI) automatically enters low power mode when no transaction target it.
12.8 Description
FIGURE 12-2:
EMBEDDED MEMORY INTERFACE BLOCK DIAGRAM
HOST
EC-to-Host Event
Host Event
EMI
Host-to-EC
EC-to-Host
Host Interrupt Source
Embedded Memory
Address
Embedded Memory Data
Memory Region 0 &
Memory Region 1
Addr
Data
Addr
Data
EC
Host-to-EC Event
The Embedded Memory Interface (EMI) is composed of a mailbox, a direct memory interface, and an Application ID
register.
The mailbox contains two registers, the HOST-to-EC Mailbox Register and the EC-to-HOST Mailbox Register, that act
as a communication portal between the system host and the embedded controller. When the HOST-to-EC Mailbox Reg-
ister is written an interrupt is generated to the embedded controller. Similarly, when the EC-to-HOST Mailbox Register
is written an interrupt is generated to the system host. The source of the system host interrupt may be read in the Inter-
rupt Source Register. These interrupt events may be individually prevented from generating a Host_SWI_Event via the
Interrupt Mask Register.
The direct memory interface, which is composed of a byte addressable 16-bit EC Address Register and a 32-bit EC
Data Register, permits the Host to read or write a portion of the EC’s internal address space. The embedded controller
may enable up to two regions of the EC’s internal address space to be exposed to the system host. The system host
may access these memory locations without intervention or assistance from the EC.
The Embedded Memory Interface can be configured so that data transfers between the Embedded Memory Interface
data bytes and the 32- bit internal address space may be multiple bytes, while Host I/O is always executed a byte at a
time.
When the Host reads one of the four bytes in the Embedded Memory Interface data register, data from the internal 32-
bit address space, at the address defined by the Embedded Memory Interface address register, is returned to the Host.
This read access will load 1, 2, or 4 bytes into the Data register depending on the configuration of the ACCESS_TYPE
bits. Similarly, writing one of the four bytes in the data register will write the corresponding byte(s) from the data register
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