MEC1404 Datasheet, PDF (120/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 4-13: SIRQ INTERRUPT CONFIGURATION REGISTER MAP (CONTINUED)
Offset
4Ch
4Dh
4Eh
4Fh
Type
R/W
R/W
R/W
R/W
Reset
FFh
FFh
FFh
FFh
IRQ12
IRQ13
IRQ14
IRQ15
Configuration Register Name
Note: A SERIRQ interrupt is deactivated by setting an entry in the SIRQ Interrupt Configuration Register Map to
FFh, which is the default reset value.
4.9.3 I/O BASE ADDRESS REGISTERS (IO_BARS)
The LPC Controller has implemented an I/O Base Address Register (BAR) for each Logical Device in the LPC Config-
uration space.
• For a description of the I/O Base Address Register format see Section 4.9.3.1, "I/O Base Address Register For-
mat," on page 120.
• For a description of the I/O BARs per Logical Device see Table 4-14, “I/O Base Address Registers,” on page 122.
On every LPC bus I/O access the unmasked portion of the programmed LPC Host Address in each of the Base Address
Registers are checked in parallel and if any matches the LPC I/O address the LPC Controller claims the bus cycle.
Note:
Software should that insure that no two I/O BARs map the same LPC I/O address. If two I/O BARs do map
to the same address, the LPC_INTERNAL_ERR and BAR_CONFLICT status bits are set when an LPC
access is targeting the address with the BAR conflict.
The format of each BAR is summarized in Section 4.9.3.1, "I/O Base Address Register Format," on page 120.
4.9.3.1 I/O Base Address Register Format
Each LPC accessible logical device has a programmable I/O Base Address Register. The following table defines the
generic format used for all of these registers. See Table 4-14, "I/O Base Address Registers" for a list of all the Logical
Device Base Address registers implemented.
Offset ^{See Table 4-14, “I/O Base Address Registers,” on page 122}
Bits
Description
31:16 LPC Host Address
These 16 bits are used to match LPC I/O addresses
15 VALID
If this bit is 1, the BAR is valid and will participate in LPC matches.
If it is 0 this BAR is ignored
Type
R/W
(Note 4
-12)
R/W
Default
See
TABLE 4-
14:
See
TABLE 4-
14:
Reset
Event
Note 4-
11
Note 4-
11
14 DEVICE (device)
R
See
Note 4-
This bit combined with FRAME constitute the Logical Device Num-
ber. DEVICE identifies the physical location of the logical device.
TABLE 4-
11
14:
This bit should always be set to 0.
DS00001956D-page 120
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