MEC1404 Datasheet, PDF (160/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 8-2: SYSTEM INTERFACE SIGNAL DESCRIPTION TABLE (CONTINUED)
Signal Name
SI_ERL
EJ_DebugM
Direction
Output
Output
Description
The SI_ERL signal represents the state of the ERL bit (2) in
the CP0 Status register. This signal indicates an error has
occurred.
The EJ_DebugM signal indicates that the processor has
entered debug mode.
Connected
at Chip-Level
No
Yes
8.4.4 ISRAM INTERFACE
The ISRAM interface is the embedded controller’s instruction fetch interface. Code Instructions may be executed from
the Instruction Memory or the Data Memory.
8.4.5 DSRAM INTERFACE
The DSRAM Interface is the embedded controller’s data interface, which can access both the Data Memory and the
Instruction Memory (literals).
8.4.6 INTERRUPT INTERFACE
The MIPS32^ M14K™ Embedded Controller is configured for External Interrupt Controller (EIC) mode.
The interrupts implemented on this chip are defined in Section 10.0, "Jump Table Vectored Interrupt Controller (JTVIC),"
on page 164. The interrupt unit generates interrupt requests (IRQs) to the CPU and has the ability to bring the CPU out
of sleep mode when a valid wake-capable interrupt request is present.
All interrupts can either be pulse or level triggered as well as having individual mask bits and priority levels.
8.5 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
8.5.1 POWER DOMAINS
8.5.2
Name
VTR
CLOCK INPUTS
DESCRIPTION
The embedded controller is powered by VTR.
Name
EC_PROC_CLK
DESCRIPTION
The EC clock is the clock source to the embedded controller.
Note: The EC clock can be throttled up or down externally by the
chip’s Power, Clocks, and Reset (PCR) circuitry.
DS00001956D-page 160
 2015 - 2016 Microchip Technology Inc.