MEC1404 Datasheet, PDF (364/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
25.0 PECI INTERFACE
25.1 Overview
The MEC140X/1X includes a PECI Interface to allow the EC to retrieve temperature readings from PECI-compliant
devices. The PECI Interface implements the PHY and Link Layer of a PECI host controller as defined in References[1]
and includes hardware support for the PECI 2.0 command set.
This chapter focuses on MEC140X/1X specific PECI Interface configuration information such as Power Domains, Clock
Inputs, Resets, Interrupts, and other chip specific information. For a functional description of the MEC140X/1X PECI
Interface refer to References [1].
25.2 References
1. PECI Interface Core, Rev. 1.31, Core-Level Architecture Specification, SMSC Confidential, 4/15/11
25.3 Terminology
No terminology has been defined for this chapter.
25.4 Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 25-1:
PECI INTERFACE I/O DIAGRAM
Host Interface
Power, Clocks and Reset
Interrupts
PECI Interface
PECI_READY
PECI_DAT
25.5 Signal Description
The Signal Description Table lists the signals that are typically routed to the pin interface.
TABLE 25-1: SIGNAL DESCRIPTION TABLE
Name
PECI_READY
PECI_DAT
Direction
Input
Input/Output
Description
PECI Ready input pin
Note: This signal is optional. If this signal is not on the pin
interface it is pulled high internally.
PECI Data signal pin
DS00001956D-page 364
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