MEC1404 Datasheet, PDF (102/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
4.5.3 RESETS
nSYSRST
Name
nSIO_RESET
LRESET#
Description
Power on Reset to the block. This signal resets all the register and logic
in this block to its default state.
This signal is used to indicate when the main power rail in the system
is reset. The LPC interface is operational when main power is present.
This signal is used to reset selected registers as defined in the Register
Interfaces descriptions.
The LRESET# signal comes from the LPC pin interface. This signal is
defined in the Intel® Low Pin Count (LPC) Interface Specification, v1.1.
The following table defines the effective reset state that result from the combination of these three reset signals.
TABLE 4-3: LPC Interface BLOCK RESET STATES
nSYSRST
(Note 4-2)
Asserted
Deasserted
LRESET#
(Note 4-1, Note 4-4)
X
Asserted
Deasserted
nSIO_RESET
(Note 4-3)
X
X
Asserted
Deasserted
Reset State
Resets all registers and logic
Resets selected registers and logic
Resets selected registers
Nothing is in Reset
Note 4-1
The EC can determine the state of the LRESET# input using registers in LPC Bus Monitor Register
on page 127.
Note 4-2
nSYSRST is asserted when VTR is turned off and is released after VTR is turned on. The nSYSRST
will be released before the System Host is expected to attempt communication over the LPC
Interface.
Note 4-3 See the individual register descriptions to determine which registers are effected by nSIO_RESET.
Note 4-4
The LPC Interface will be ready to receive a new transaction when LRESET# is deasserted. See the
individual register descriptions to determine which registers are effected by this reset.
In system, the LPC Interface is required to be operational in ACPI Sleep States S0 - S2. When the system enters Sleep
States S3 - S5 the LPC interface must tristate its outputs. The following table shows the behavior of LPC output and
input/output signals under reset conditions.
TABLE 4-4: LPC INTERFACE SIGNALS BEHAVIOR ON RESET
Pins
LAD[3:0]
SERIRQ
CLKRUN#
nSYSRST
Tri-state
Tri-state
Tri-state
nSIO_RESET
Tri-state
Tri-state
Tri-state
LPCPD#
Tri-state
Tri-state
Tri-state
LRESET#
Asserted
Tri-State
Tri-State
Tri-State
DS00001956D-page 102
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