MEC1404 Datasheet, PDF (527/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 43-24: PS/2 CHANNEL TRANSMISSION TIMING PARAMETERS (CONTINUED)
Name
Description
MIN
t10
Duration of Data Frame. Falling edge of
Start bit CLK (1st clk) to falling edge of
Parity bit CLK (10th clk).
t11 DATA output by MEC140X/1X following
the falling edge of CLK. The auxiliary
peripheral device samples DATA follow-
ing the rising edge of CLK.
t12 Rising edge following the 11th falling
3.5
clock edge to PS_T/R bit driven low.
t13 Trailing edge of PS_T/R to XMIT_IDLE bit
asserted.
t14 DATA released to high-Z following the
PS2_T/R bit going low.
t15 XMIT_IDLE bit driven high to interrupt
generated.
Note1- Interrupt is cleared by writing a 1
to the status bit in the GIRQ17 source
register.
t17 Trailing edge of CLK is held low prior to
going high-Z
TYP
MAX
2.002
1.0
7.1
500
Units
ms
µs
µs
ns
FIGURE 43-24: PS/2 RECEIVE TIMING
PS2_CLK
PS2_DATA
PS2_EN
PS2_T/R
RDATA_RDY
Read Rx Reg
Interrupt
t7
t3
t2
t4
t5
t1
t6
D0 D1 D2 D3 D4 D5 D6 D7 P S
t8
t12
t10
t11
t9
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