MEC1404 Datasheet, PDF (131/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
4.11.7 DEVICE MEMORY BAR INHIBIT REGISTER
Offset ^40h
Bits
Description
Type
63:0 Device Mem BAR_Inhibit[63:0]
R/W
When bit i of the Device Mem BAR_Inhibit[63:0] field is asserted
(‘1’), where i is the logical device number of one of the Device
Memory Base Address Registers, the BAR for the associated
device is disabled and its LPC Memory addresses will not be
claimed on the LPC bus, independent of the value of the Valid bit in
the BAR.
When bit i is not asserted (default), BAR activity for the Logical
Device is based on the Valid bit in the BAR.
All of the Device Mem BAR_Inhibit[63:0] bits are R/W and have no
affect on reserved logical device numbers.
Default
0h
Reset
Event
nSYSR
ST
4.11.8 SRAM MEMORY HOST CONFIGURATION REGISTER
Offset ^FCh
Bits
Description
Type
31:8 AHB Base
These 24 bits define the base of a region in AHB address space that
will be mapped to the LPC Memory space. Valid AHB addresses are
integer multiples ot the memory size. For example, if the memory is
4k bytes than the AHB Base address must be located on a 4k byte
boundary.
Note:
The 24 bits in this field are left-shited by 8 bits to form a
32-bit AHB address, so all memory blocks begin on a
256-byte boundary.
7 Inhibit
Host access to the memory block is inhibited when this bit is 1. The
Host can access the memory region mapped by the fields AHB Base
and Size when this bit is 0.
6:4 RESERVED
3:0 Size
The number of address bits to pass unchanged when translating an
LPC address to an AHB address. These 4 bits in effect define the
size of the block to be claimed by the LPC bridge, defined as a
power of 2. A value of 0 defines a 2⁰ or a 1-byte region starting at
LPC Host Address. A value of 12 defines a 2¹² or a 4K-byte region.
Values larger than 12 are undefined..
R/W
R/W
RES
R/W
Default
0h
Reset
Event
nSYSRS
T
0h
nSYSRS
T
-
-
0h
nSYSRS
T
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DS00001956D-page 131