MEC1404 Datasheet, PDF (12/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
2.0 PIN CONFIGURATION
2.1 Description
The Pin Configuration chapter includes Pin Lists, Pin Description, Pin Multiplexing, Notes for Tables in this Chapter, Pin
States After VTR Power-On, and Packages.
2.2 Terminology and Symbols for Pins/Buffers
2.2.1 BUFFER TERMINOLOGY
Term
Definition
Pin Ref. Number There is a unique reference number for each pin name.
#
The ‘#’ sign at the end of a signal name indicates an active-low signal
n
The lowercase ‘n’ preceding a signal name indicates an active-low signal
PWR
Power
I
IS
I_AN
O
OD
IO
Digital Input
Input with Schmitt Trigger
Analog Input
Push-Pull Output
Open Drain Output
Bi-directional pin
IOD
Bi-directional pin with Open Drain Output
PIO
PCI_I
PCI_O
PCI_OD
Programmable as Input, Output, Open Drain Output, Bi-directional or Bi-directional with Open
Drain Output.
Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 2-1)
Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 2-1)
Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 2-1)
PCI_IO
Input/Output These pins meet the PCI 3.3V AC and DC Characteristics. (Note 2-1)
PCI_ICLK
Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2-2)
PCI_PIO
Programmable as Input, Output, Open Drain Output, Bi-directional or Bi-directional with Open
Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 2-1).
PECI_IO
PECI Input/Output. These pins operate at the processor voltage level (VREF_CPU)
SB-TSI
SB-TSI Input/Output. These pins operate at the processor voltage level (VREF_CPU)
Note 2-1 See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.
Note 2-2 See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.
2.2.2 PIN NAMING CONVENTIONS
1. Pin Name is composed of the multiplexed options separated by ‘/’. E.g., GPIOxxxx/SignalA/SignalB.
2. The first signal shown in a pin name is the default signal. E.g., GPIOxxxx/SignalA/SignalB means the GPIO is
the default signal.
3. Parenthesis ‘()’ are used to list aliases or alternate functionality for a single mux option. E.g. GPIOxxx(Alias)/Sig-
nalA/SignalB. The Alias is the intended usage for a specific GPIO. E.g., GPIOxxx(ICSP_DATA) is intended to
indicate that ICSP_DATA signal may come out on this pin when the Mux Control is set for GPIOxxx. In this case,
enabling the test mode takes precedence over the Mux Control selection.
4. Square brackets ‘[ ]’ are used to indicate there is a Strap Option on a pin. This is always shown as the last signal
on the Pin Name.
5. Signal Names appended with a numeric value indicates the Instance Number, except for SMBus Pins. E.g.,
PWM0, PWM1, etc. indicates that PWM0 is the PWM output for PWM Instance 0, PWM1 is the PWM output for
PWM Instance 1, etc. Note that this same instance number is shown in the Register Base Address tables linking
the specific PWM block instance to a specific signal on the pinout. The instance number may be omitted if there
in only one instance of the IP block implemented.
DS00001956D-page 12
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