MEC1404 Datasheet, PDF (440/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^20h
Bits
0 JTAG_EN
Description
This bit enables the JTAG debug port.
0 = JTAG port disabled. JTAG cannot be enabled (i.e., the TRST#
pin is ignored and the JTAG signals remain in their non-JTAG
state).
1= JTAG port enabled. A high on TRST# enables JTAG
Type
R/W
Default
0b
Reset
Event
nSYSRST
34.8.4 WDT EVENT COUNT
Offset ^28h
Bits
31:4 Reserved
3:0 WDT_COUNT
Description
Type
R
R/W
34.8.5
These EC R/W bits are cleared to 0 on VTR POR, but not on a
WDT.
Note:
This field is written by Boot ROM firmware to indicate the
number of times a WDT fired before loading a good EC
code image.
VREF_CPU DISABLE
Offset ^40h
Bits
31:7 Reserved
6:2 Test
1 VREF_CPU Disable
Description
Type
R
R/W
R/W
0: Enable
1: Disable
Note:
In order to achieve the lowest leakage current when both
PECI and SB TSI are not used, set the VREF_CPU Dis-
able bit to 1.
0 Test
R
Default
-
0b
Reset
Event
-
VTR_RE-
SET#
Default
-
0b
0b
Reset
Event
-
nSYSRST
nSYSRST
0b
nSYSRST
DS00001956D-page 440
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