MEC1404 Datasheet, PDF (124/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^{See Table 4-15, “Device Memory Base Address Registers,” on page 124}
Bits
Description
Type
13:8 FRAME
These 6 bits are used to specify a logical device frame number
within a bus. This field is multiplied by 400h to provide the frame
address within the peripheral bus address. Frame values for
frames corresponding to logical devices that are not present on the
device are invalid.
R or
R/W
(see
Note 3)
7:0 MASK
R or
These 8 bits are used to mask off address bits in the address
match between an LPC I/O address and the Host Address field of
the BARs, as described in Section 4.8.2.2, "Device Memory Trans-
R/W
(see
Note 3)
actions". A block of up to 256 8-bit registers can be assigned to
one base address.
Default
See
TABLE 4-
15:
See
TABLE 4-
15:
Reset
Event
nSIO_
RESET
nSIO_
RESET
3: The Mask and Frame fields of all logical devices are read-only except for 3h (ACPI EC Channel 0).
4.9.6.2 Device Memory Base Address Register Table
The table below lists the Base Address Registers for logical devices which have LPC memory access in this device.
LPC Memory cycle access is controlled by LPC Memory Base Address Registers. LPC Memory BAR registers are
located in LDN Ch (LPC Interface) at AHB base address 000F_3300h starting at the offset shown in the Device Memory
Base Address Registers table.
.
TABLE 4-15: DEVICE MEMORY BASE ADDRESS REGISTERS
Offset
Logical
Device
Number
(hex)
C0h
0
C6h
3
CCh
4
D2h
9
D8h
A
DEh
B
Logical Devices
EMI 0
ACPI EC0
ACPI EC1
Mailbox Interface
ACPI EC2
ACPI EC3
Base Address Register Bit Field Descriptions
Bits
Bits
Bits
[D47:D16] Bit [D15] Bit [D14] [D13:D8] [D6:D0]
Default
LPC Mem
Host
MASK
Reset Default Address VALID DEVICE FRAME (Note 2)
0000_0000_00
0F
0000_0000
0
0
0
F
0000_0062_03
04
0000_0062
0
0
3
4
0000_0066_04
07
0000_0066
0
0
4
7
0000_0000_09
01
0000_0000
0
0
9
1
0000_0000_0A
07
0000_0000
0
0
A
7
0000_0000_0B
07
0000_0000
0
0
B
7
Note 1: The FRAME and MASK fields for these Legacy devices are not used to determine which LPC Memory addresses to
claim. The address range match is maintained within the blocks themselves.
Note 2: The ACPI-ECx Mask bit field is a read/write bit field. All other MASK bit fields are read-only as defined in the register
DS00001956D-page 124
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