MEC1404 Datasheet, PDF (359/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^10h
Bits
Description
Type
5 BUSY
RO
This is a status signal.
1=The DMA Channel is busy (FSM is not IDLE)
0=The DMA Channel is not busy (FSM is IDLE)
4:3 STATUS
R
This is a status signal. The status decode is listed in priority order
with the highest priority first.
3: Error detected by the DMA
2: The DMA Channel is externally done, in that the Device has termi-
nated the transfer over the Hardware Flow Control through the
Port dma_term
1: The DMA Channel is locally done, in that Memory Start Address
equals Memory End Address
0: DMA Channel Control:Run is Disabled (0x0)
Note: This functionality has been replaced by the Interrupt field,
and as such should never be used.
The field will not flag back appropriately timed status, and
if used may cause the firmware to become out-of-sync
with the hardware.
This field has multiple non-exclusive statuses, but may
only display a single status. As such, multiple statuses
may be TRUE, but this will appear as though only a single
status has been triggered.
2 DONE
RO
This is a status signal. It is only valid while DMA Channel Con-
trol:Run is Enabled. This is the inverse of the DMA Channel Con-
trol:Busy field, except this is qualified with the DMA Channel
Control:Run field.
1=Channel is done
0=Channel is not done or it is OFF
1 REQUEST
RO
This is a status field.
1: There is a transfer request from the Master Device
0: There is no transfer request from the Master Device
0 RUN
RW
This is a control field.
Note:
This bit only applies to Hardware Flow Control mode.
Do not use this bit in conjunction with the Firmware Flow
Control.
1: This channel is enabled and will service transfer requests
0=This channel is disabled. All transfer requests are ignored
Default
0h
Reset
Event
DMA_R
ESET
0h
DMA_R
ESET
0h
DMA_R
ESET
0h
DMA_R
ESET
0h
DMA_R
ESET
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DS00001956D-page 359