MEC1404 Datasheet, PDF (457/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
37.9.2 LATCH ENABLE REGISTER
Offset ^04h
Bits
DESCRIPTION
31:2 Reserved
1:0 LE
Latching Enables. Latching occurs after the Polarity con-
figuration, so a VCI_IN# pin is asserted when it is ‘0’ if
VCI_IN_POL is ‘0’, and asserted when it is ‘1 ‘if
VCI_IN_POL is ‘1’.
For each bit in the field:
1=Enabled. Assertions of the VCI_IN# pin are held until
the latch is reset by writing the corresponding LS bit
0=Not Enabled. The VCI_IN# signal is not latched but
passed directly to the VCI_OUT logic
37.9.3 LATCH RESETS REGISTER
TYPE
R
R/W
DEFAULT
-
00h
RESET
EVENT
-
VBAT_POR
Offset ^08h
Bits
DESCRIPTION
31:2 Reserved
1:0 LS
Latch Resets. When a Latch Resets bit is written with a ‘1’,
the corresponding VCI_IN# latch is de-asserted (‘1’).
The VCI_IN# input to the latch has priority over the Latch
Reset input, so firmware cannot reset the latch while the
VCI_IN# pin is asserted. Firmware should sample the
state of the pin in the VCI Register before attempting to
reset the latch. As noted in the Latch Enable Register, the
assertion level is determined by the VCI_IN_POL bit.
Reads of this register are undefined.
TYPE
R
W
DEFAULT
-
–
RESET
EVENT
-
–
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DS00001956D-page 457